//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
//
//  File Revision       : 132916
//
//  Date                :  2012-07-02 13:38:10 +0100 (Mon, 02 Jul 2012)
//
//  Release Information : PL401-r0p1-00eac0
//
//------------------------------------------------------------------------------
//  File Purpose        : Structural file to implement a single
//                        build layers module of a multi layer 
//                        AXI bus matrix 
//   
//  Key Configuration Details-
//      - Slave Interface number : 0
//      - Connected to 9 master interfaces
//
// Notes on port naming conventions- 
//
//     All AXI point to point connections can be considered a 
//     MasterInterface - SlaveInterface connection. 
//
//     The AXI ports on the NIC400 A3BM are named as follows-  
//
//     *_m<n> suffix to denote a MasterIf (connect to external AXI slave)
//     *_s0 suffix to denote the SlaveIf  (connect to external AXI master) 
//
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Module Declaration
//------------------------------------------------------------------------------

module nic400_switch2_ml_blayer_0_ysyx_rv32
  (
    // SlaveInterface Port

    // Write Address Channel
    awuser_s,
    awid_s,
    awaddr_s,
    awlen_s,
    awsize_s,
    awburst_s,
    awlock_s,
    awcache_s,
    awprot_s,
    awvalid_s,
    awvalid_vect_s,
    awready_s,
    aw_qv_s,
   
    // Write Channel
    wdata_s,
    wstrb_s,
    wlast_s,
    wvalid_s,
    wready_s,

    // Write Response Channel
    bid_s,
    bresp_s,
    bvalid_s,
    bready_s,

    // Read Address Channel
    aruser_s,
    arid_s,
    araddr_s,
    arlen_s,
    arsize_s,
    arburst_s,
    arlock_s,
    arcache_s,
    arprot_s,
    arvalid_s,
    arvalid_vect_s,
    arready_s,
    ar_qv_s,
   
    // Read Channel
    rid_s,
    rdata_s,
    rresp_s,
    rlast_s,
    rvalid_s,
    rready_s,


    // Master Interface 0 Port

    // Write Address Channel
    awuser_m0,
    awid_m0,
    awaddr_m0,
    awlen_m0,
    awsize_m0,
    awburst_m0,
    awlock_m0,
    awcache_m0,
    awprot_m0,
    awvalid_m0,
    awvalid_vect_m0,
    awready_m0,
    aw_qv_m0,
   
    // Write Channel
    wdata_m0,
    wstrb_m0,
    wlast_m0,
    wvalid_m0,
    wready_m0,

    // Write Response Channel
    bid_m0,
    bresp_m0,
    bvalid_m0,
    bready_m0,

    // Read Address Channel
    aruser_m0,
    arid_m0,
    araddr_m0,
    arlen_m0,
    arsize_m0,
    arburst_m0,
    arlock_m0,
    arcache_m0,
    arprot_m0,
    arvalid_m0,
    arvalid_vect_m0,
    arready_m0,
    ar_qv_m0,
   
    // Read Channel
    rid_m0,
    rdata_m0,
    rresp_m0,
    rlast_m0,
    rvalid_m0,
    rready_m0,
    // Master Interface 1 Port

    // Write Address Channel
    awuser_m1,
    awid_m1,
    awaddr_m1,
    awlen_m1,
    awsize_m1,
    awburst_m1,
    awlock_m1,
    awcache_m1,
    awprot_m1,
    awvalid_m1,
    awvalid_vect_m1,
    awready_m1,
    aw_qv_m1,
   
    // Write Channel
    wdata_m1,
    wstrb_m1,
    wlast_m1,
    wvalid_m1,
    wready_m1,

    // Write Response Channel
    bid_m1,
    bresp_m1,
    bvalid_m1,
    bready_m1,

    // Read Address Channel
    aruser_m1,
    arid_m1,
    araddr_m1,
    arlen_m1,
    arsize_m1,
    arburst_m1,
    arlock_m1,
    arcache_m1,
    arprot_m1,
    arvalid_m1,
    arvalid_vect_m1,
    arready_m1,
    ar_qv_m1,
   
    // Read Channel
    rid_m1,
    rdata_m1,
    rresp_m1,
    rlast_m1,
    rvalid_m1,
    rready_m1,
    // Master Interface 2 Port

    // Write Address Channel
    awuser_m2,
    awid_m2,
    awaddr_m2,
    awlen_m2,
    awsize_m2,
    awburst_m2,
    awlock_m2,
    awcache_m2,
    awprot_m2,
    awvalid_m2,
    awvalid_vect_m2,
    awready_m2,
    aw_qv_m2,
   
    // Write Channel
    wdata_m2,
    wstrb_m2,
    wlast_m2,
    wvalid_m2,
    wready_m2,

    // Write Response Channel
    bid_m2,
    bresp_m2,
    bvalid_m2,
    bready_m2,

    // Read Address Channel
    aruser_m2,
    arid_m2,
    araddr_m2,
    arlen_m2,
    arsize_m2,
    arburst_m2,
    arlock_m2,
    arcache_m2,
    arprot_m2,
    arvalid_m2,
    arvalid_vect_m2,
    arready_m2,
    ar_qv_m2,
   
    // Read Channel
    rid_m2,
    rdata_m2,
    rresp_m2,
    rlast_m2,
    rvalid_m2,
    rready_m2,
    // Master Interface 3 Port

    // Write Address Channel
    awuser_m3,
    awid_m3,
    awaddr_m3,
    awlen_m3,
    awsize_m3,
    awburst_m3,
    awlock_m3,
    awcache_m3,
    awprot_m3,
    awvalid_m3,
    awvalid_vect_m3,
    awready_m3,
    aw_qv_m3,
   
    // Write Channel
    wdata_m3,
    wstrb_m3,
    wlast_m3,
    wvalid_m3,
    wready_m3,

    // Write Response Channel
    bid_m3,
    bresp_m3,
    bvalid_m3,
    bready_m3,

    // Read Address Channel
    aruser_m3,
    arid_m3,
    araddr_m3,
    arlen_m3,
    arsize_m3,
    arburst_m3,
    arlock_m3,
    arcache_m3,
    arprot_m3,
    arvalid_m3,
    arvalid_vect_m3,
    arready_m3,
    ar_qv_m3,
   
    // Read Channel
    rid_m3,
    rdata_m3,
    rresp_m3,
    rlast_m3,
    rvalid_m3,
    rready_m3,
    // Master Interface 4 Port

    // Write Address Channel
    awuser_m4,
    awid_m4,
    awaddr_m4,
    awlen_m4,
    awsize_m4,
    awburst_m4,
    awlock_m4,
    awcache_m4,
    awprot_m4,
    awvalid_m4,
    awvalid_vect_m4,
    awready_m4,
    aw_qv_m4,
   
    // Write Channel
    wdata_m4,
    wstrb_m4,
    wlast_m4,
    wvalid_m4,
    wready_m4,

    // Write Response Channel
    bid_m4,
    bresp_m4,
    bvalid_m4,
    bready_m4,

    // Read Address Channel
    aruser_m4,
    arid_m4,
    araddr_m4,
    arlen_m4,
    arsize_m4,
    arburst_m4,
    arlock_m4,
    arcache_m4,
    arprot_m4,
    arvalid_m4,
    arvalid_vect_m4,
    arready_m4,
    ar_qv_m4,
   
    // Read Channel
    rid_m4,
    rdata_m4,
    rresp_m4,
    rlast_m4,
    rvalid_m4,
    rready_m4,
    // Master Interface 5 Port

    // Write Address Channel
    awuser_m5,
    awid_m5,
    awaddr_m5,
    awlen_m5,
    awsize_m5,
    awburst_m5,
    awlock_m5,
    awcache_m5,
    awprot_m5,
    awvalid_m5,
    awvalid_vect_m5,
    awready_m5,
    aw_qv_m5,
   
    // Write Channel
    wdata_m5,
    wstrb_m5,
    wlast_m5,
    wvalid_m5,
    wready_m5,

    // Write Response Channel
    bid_m5,
    bresp_m5,
    bvalid_m5,
    bready_m5,

    // Read Address Channel
    aruser_m5,
    arid_m5,
    araddr_m5,
    arlen_m5,
    arsize_m5,
    arburst_m5,
    arlock_m5,
    arcache_m5,
    arprot_m5,
    arvalid_m5,
    arvalid_vect_m5,
    arready_m5,
    ar_qv_m5,
   
    // Read Channel
    rid_m5,
    rdata_m5,
    rresp_m5,
    rlast_m5,
    rvalid_m5,
    rready_m5,
    // Master Interface 6 Port

    // Write Address Channel
    awuser_m6,
    awid_m6,
    awaddr_m6,
    awlen_m6,
    awsize_m6,
    awburst_m6,
    awlock_m6,
    awcache_m6,
    awprot_m6,
    awvalid_m6,
    awvalid_vect_m6,
    awready_m6,
    aw_qv_m6,
   
    // Write Channel
    wdata_m6,
    wstrb_m6,
    wlast_m6,
    wvalid_m6,
    wready_m6,

    // Write Response Channel
    bid_m6,
    bresp_m6,
    bvalid_m6,
    bready_m6,

    // Read Address Channel
    aruser_m6,
    arid_m6,
    araddr_m6,
    arlen_m6,
    arsize_m6,
    arburst_m6,
    arlock_m6,
    arcache_m6,
    arprot_m6,
    arvalid_m6,
    arvalid_vect_m6,
    arready_m6,
    ar_qv_m6,
   
    // Read Channel
    rid_m6,
    rdata_m6,
    rresp_m6,
    rlast_m6,
    rvalid_m6,
    rready_m6,
    // Master Interface 7 Port

    // Write Address Channel
    awuser_m7,
    awid_m7,
    awaddr_m7,
    awlen_m7,
    awsize_m7,
    awburst_m7,
    awlock_m7,
    awcache_m7,
    awprot_m7,
    awvalid_m7,
    awvalid_vect_m7,
    awready_m7,
    aw_qv_m7,
   
    // Write Channel
    wdata_m7,
    wstrb_m7,
    wlast_m7,
    wvalid_m7,
    wready_m7,

    // Write Response Channel
    bid_m7,
    bresp_m7,
    bvalid_m7,
    bready_m7,

    // Read Address Channel
    aruser_m7,
    arid_m7,
    araddr_m7,
    arlen_m7,
    arsize_m7,
    arburst_m7,
    arlock_m7,
    arcache_m7,
    arprot_m7,
    arvalid_m7,
    arvalid_vect_m7,
    arready_m7,
    ar_qv_m7,
   
    // Read Channel
    rid_m7,
    rdata_m7,
    rresp_m7,
    rlast_m7,
    rvalid_m7,
    rready_m7,
    // Master Interface 8 Port

    // Write Address Channel
    awuser_m8,
    awid_m8,
    awaddr_m8,
    awlen_m8,
    awsize_m8,
    awburst_m8,
    awlock_m8,
    awcache_m8,
    awprot_m8,
    awvalid_m8,
    awvalid_vect_m8,
    awready_m8,
    aw_qv_m8,
   
    // Write Channel
    wdata_m8,
    wstrb_m8,
    wlast_m8,
    wvalid_m8,
    wready_m8,

    // Write Response Channel
    bid_m8,
    bresp_m8,
    bvalid_m8,
    bready_m8,

    // Read Address Channel
    aruser_m8,
    arid_m8,
    araddr_m8,
    arlen_m8,
    arsize_m8,
    arburst_m8,
    arlock_m8,
    arcache_m8,
    arprot_m8,
    arvalid_m8,
    arvalid_vect_m8,
    arready_m8,
    ar_qv_m8,
   
    // Read Channel
    rid_m8,
    rdata_m8,
    rresp_m8,
    rlast_m8,
    rvalid_m8,
    rready_m8,
  // Miscelaneous connections
    aclk,
    aresetn
  );

  // ---------------------------------------------------------------------------
  //  parameters
  // ---------------------------------------------------------------------------

  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------

  // SlaveInterface Port
  // Write Address Channel
  input [3:0]       awuser_s;
  input [3:0]       awid_s;
  input [31:0]      awaddr_s;
  input [7:0]       awlen_s;
  input [2:0]       awsize_s;
  input [1:0]       awburst_s;
  input             awlock_s;
  input [3:0]       awcache_s;
  input [2:0]       awprot_s;
  input             awvalid_s;
  input [8:0]            awvalid_vect_s;
  output            awready_s;
  input [3:0]       aw_qv_s;

  // Write Channel
  input  [31:0]     wdata_s;
  input  [3:0]      wstrb_s;
  input             wlast_s;
  input             wvalid_s;
  output            wready_s;

  // Write Response Channel
  output [3:0]      bid_s;
  output [1:0]      bresp_s;
  output            bvalid_s;
  input             bready_s;

  // Read Address Channel
  input [3:0]       aruser_s;
  input [3:0]       arid_s;
  input [31:0]      araddr_s;
  input [7:0]       arlen_s;
  input [2:0]       arsize_s;
  input [1:0]       arburst_s;
  input             arlock_s;
  input [3:0]       arcache_s;
  input [2:0]       arprot_s;
  input             arvalid_s;
  input [8:0]            arvalid_vect_s;
  output            arready_s;
  input [3:0]       ar_qv_s;

  // Read Channel
  output [3:0]      rid_s;
  output [31:0]     rdata_s;
  output [1:0]      rresp_s;
  output            rlast_s;
  output            rvalid_s;
  input             rready_s;

  // Master Interface 0 Port

  // Write Address Channel
  output [3:0]                      awuser_m0;
  output [3:0]      awid_m0;
  output [31:0]     awaddr_m0;
  output [7:0]      awlen_m0;
  output [2:0]      awsize_m0;
  output [1:0]      awburst_m0;
  output            awlock_m0;
  output [3:0]      awcache_m0;
  output [2:0]      awprot_m0;
  output            awvalid_m0;
  output           awvalid_vect_m0;
  input             awready_m0;
  output [3:0]      aw_qv_m0;
   
  // Write Channel
  output  [31:0]    wdata_m0;
  output  [3:0]     wstrb_m0;
  output            wlast_m0;
  output            wvalid_m0;
  input             wready_m0;

  // Write Response Channel
  input [3:0]       bid_m0;
  input [1:0]       bresp_m0;
  input             bvalid_m0;
  output            bready_m0;

  // Read Address Channel
  output  [3:0]          aruser_m0;
  output  [3:0]     arid_m0;
  output  [31:0]    araddr_m0;
  output  [7:0]     arlen_m0;
  output  [2:0]     arsize_m0;
  output  [1:0]     arburst_m0;
  output            arlock_m0;
  output  [3:0]     arcache_m0;
  output  [2:0]     arprot_m0;
  output            arvalid_m0;
  output            arvalid_vect_m0;
  input             arready_m0;
  output  [3:0]     ar_qv_m0;
   
  // Read Channel
  input [3:0]       rid_m0;
  input [31:0]      rdata_m0;
  input [1:0]       rresp_m0;
  input             rlast_m0;
  input             rvalid_m0;
  output            rready_m0;

  // Master Interface 1 Port

  // Write Address Channel
  output [3:0]                      awuser_m1;
  output [3:0]      awid_m1;
  output [31:0]     awaddr_m1;
  output [7:0]      awlen_m1;
  output [2:0]      awsize_m1;
  output [1:0]      awburst_m1;
  output            awlock_m1;
  output [3:0]      awcache_m1;
  output [2:0]      awprot_m1;
  output            awvalid_m1;
  output           awvalid_vect_m1;
  input             awready_m1;
  output [3:0]      aw_qv_m1;
   
  // Write Channel
  output  [31:0]    wdata_m1;
  output  [3:0]     wstrb_m1;
  output            wlast_m1;
  output            wvalid_m1;
  input             wready_m1;

  // Write Response Channel
  input [3:0]       bid_m1;
  input [1:0]       bresp_m1;
  input             bvalid_m1;
  output            bready_m1;

  // Read Address Channel
  output  [3:0]          aruser_m1;
  output  [3:0]     arid_m1;
  output  [31:0]    araddr_m1;
  output  [7:0]     arlen_m1;
  output  [2:0]     arsize_m1;
  output  [1:0]     arburst_m1;
  output            arlock_m1;
  output  [3:0]     arcache_m1;
  output  [2:0]     arprot_m1;
  output            arvalid_m1;
  output            arvalid_vect_m1;
  input             arready_m1;
  output  [3:0]     ar_qv_m1;
   
  // Read Channel
  input [3:0]       rid_m1;
  input [31:0]      rdata_m1;
  input [1:0]       rresp_m1;
  input             rlast_m1;
  input             rvalid_m1;
  output            rready_m1;

  // Master Interface 2 Port

  // Write Address Channel
  output [3:0]                      awuser_m2;
  output [3:0]      awid_m2;
  output [31:0]     awaddr_m2;
  output [7:0]      awlen_m2;
  output [2:0]      awsize_m2;
  output [1:0]      awburst_m2;
  output            awlock_m2;
  output [3:0]      awcache_m2;
  output [2:0]      awprot_m2;
  output            awvalid_m2;
  output           awvalid_vect_m2;
  input             awready_m2;
  output [3:0]      aw_qv_m2;
   
  // Write Channel
  output  [31:0]    wdata_m2;
  output  [3:0]     wstrb_m2;
  output            wlast_m2;
  output            wvalid_m2;
  input             wready_m2;

  // Write Response Channel
  input [3:0]       bid_m2;
  input [1:0]       bresp_m2;
  input             bvalid_m2;
  output            bready_m2;

  // Read Address Channel
  output  [3:0]          aruser_m2;
  output  [3:0]     arid_m2;
  output  [31:0]    araddr_m2;
  output  [7:0]     arlen_m2;
  output  [2:0]     arsize_m2;
  output  [1:0]     arburst_m2;
  output            arlock_m2;
  output  [3:0]     arcache_m2;
  output  [2:0]     arprot_m2;
  output            arvalid_m2;
  output            arvalid_vect_m2;
  input             arready_m2;
  output  [3:0]     ar_qv_m2;
   
  // Read Channel
  input [3:0]       rid_m2;
  input [31:0]      rdata_m2;
  input [1:0]       rresp_m2;
  input             rlast_m2;
  input             rvalid_m2;
  output            rready_m2;

  // Master Interface 3 Port

  // Write Address Channel
  output [3:0]                      awuser_m3;
  output [3:0]      awid_m3;
  output [31:0]     awaddr_m3;
  output [7:0]      awlen_m3;
  output [2:0]      awsize_m3;
  output [1:0]      awburst_m3;
  output            awlock_m3;
  output [3:0]      awcache_m3;
  output [2:0]      awprot_m3;
  output            awvalid_m3;
  output           awvalid_vect_m3;
  input             awready_m3;
  output [3:0]      aw_qv_m3;
   
  // Write Channel
  output  [31:0]    wdata_m3;
  output  [3:0]     wstrb_m3;
  output            wlast_m3;
  output            wvalid_m3;
  input             wready_m3;

  // Write Response Channel
  input [3:0]       bid_m3;
  input [1:0]       bresp_m3;
  input             bvalid_m3;
  output            bready_m3;

  // Read Address Channel
  output  [3:0]          aruser_m3;
  output  [3:0]     arid_m3;
  output  [31:0]    araddr_m3;
  output  [7:0]     arlen_m3;
  output  [2:0]     arsize_m3;
  output  [1:0]     arburst_m3;
  output            arlock_m3;
  output  [3:0]     arcache_m3;
  output  [2:0]     arprot_m3;
  output            arvalid_m3;
  output            arvalid_vect_m3;
  input             arready_m3;
  output  [3:0]     ar_qv_m3;
   
  // Read Channel
  input [3:0]       rid_m3;
  input [31:0]      rdata_m3;
  input [1:0]       rresp_m3;
  input             rlast_m3;
  input             rvalid_m3;
  output            rready_m3;

  // Master Interface 4 Port

  // Write Address Channel
  output [3:0]                      awuser_m4;
  output [3:0]      awid_m4;
  output [31:0]     awaddr_m4;
  output [7:0]      awlen_m4;
  output [2:0]      awsize_m4;
  output [1:0]      awburst_m4;
  output            awlock_m4;
  output [3:0]      awcache_m4;
  output [2:0]      awprot_m4;
  output            awvalid_m4;
  output           awvalid_vect_m4;
  input             awready_m4;
  output [3:0]      aw_qv_m4;
   
  // Write Channel
  output  [31:0]    wdata_m4;
  output  [3:0]     wstrb_m4;
  output            wlast_m4;
  output            wvalid_m4;
  input             wready_m4;

  // Write Response Channel
  input [3:0]       bid_m4;
  input [1:0]       bresp_m4;
  input             bvalid_m4;
  output            bready_m4;

  // Read Address Channel
  output  [3:0]          aruser_m4;
  output  [3:0]     arid_m4;
  output  [31:0]    araddr_m4;
  output  [7:0]     arlen_m4;
  output  [2:0]     arsize_m4;
  output  [1:0]     arburst_m4;
  output            arlock_m4;
  output  [3:0]     arcache_m4;
  output  [2:0]     arprot_m4;
  output            arvalid_m4;
  output            arvalid_vect_m4;
  input             arready_m4;
  output  [3:0]     ar_qv_m4;
   
  // Read Channel
  input [3:0]       rid_m4;
  input [31:0]      rdata_m4;
  input [1:0]       rresp_m4;
  input             rlast_m4;
  input             rvalid_m4;
  output            rready_m4;

  // Master Interface 5 Port

  // Write Address Channel
  output [3:0]                      awuser_m5;
  output [3:0]      awid_m5;
  output [31:0]     awaddr_m5;
  output [7:0]      awlen_m5;
  output [2:0]      awsize_m5;
  output [1:0]      awburst_m5;
  output            awlock_m5;
  output [3:0]      awcache_m5;
  output [2:0]      awprot_m5;
  output            awvalid_m5;
  output           awvalid_vect_m5;
  input             awready_m5;
  output [3:0]      aw_qv_m5;
   
  // Write Channel
  output  [31:0]    wdata_m5;
  output  [3:0]     wstrb_m5;
  output            wlast_m5;
  output            wvalid_m5;
  input             wready_m5;

  // Write Response Channel
  input [3:0]       bid_m5;
  input [1:0]       bresp_m5;
  input             bvalid_m5;
  output            bready_m5;

  // Read Address Channel
  output  [3:0]          aruser_m5;
  output  [3:0]     arid_m5;
  output  [31:0]    araddr_m5;
  output  [7:0]     arlen_m5;
  output  [2:0]     arsize_m5;
  output  [1:0]     arburst_m5;
  output            arlock_m5;
  output  [3:0]     arcache_m5;
  output  [2:0]     arprot_m5;
  output            arvalid_m5;
  output            arvalid_vect_m5;
  input             arready_m5;
  output  [3:0]     ar_qv_m5;
   
  // Read Channel
  input [3:0]       rid_m5;
  input [31:0]      rdata_m5;
  input [1:0]       rresp_m5;
  input             rlast_m5;
  input             rvalid_m5;
  output            rready_m5;

  // Master Interface 6 Port

  // Write Address Channel
  output [3:0]                      awuser_m6;
  output [3:0]      awid_m6;
  output [31:0]     awaddr_m6;
  output [7:0]      awlen_m6;
  output [2:0]      awsize_m6;
  output [1:0]      awburst_m6;
  output            awlock_m6;
  output [3:0]      awcache_m6;
  output [2:0]      awprot_m6;
  output            awvalid_m6;
  output           awvalid_vect_m6;
  input             awready_m6;
  output [3:0]      aw_qv_m6;
   
  // Write Channel
  output  [31:0]    wdata_m6;
  output  [3:0]     wstrb_m6;
  output            wlast_m6;
  output            wvalid_m6;
  input             wready_m6;

  // Write Response Channel
  input [3:0]       bid_m6;
  input [1:0]       bresp_m6;
  input             bvalid_m6;
  output            bready_m6;

  // Read Address Channel
  output  [3:0]          aruser_m6;
  output  [3:0]     arid_m6;
  output  [31:0]    araddr_m6;
  output  [7:0]     arlen_m6;
  output  [2:0]     arsize_m6;
  output  [1:0]     arburst_m6;
  output            arlock_m6;
  output  [3:0]     arcache_m6;
  output  [2:0]     arprot_m6;
  output            arvalid_m6;
  output            arvalid_vect_m6;
  input             arready_m6;
  output  [3:0]     ar_qv_m6;
   
  // Read Channel
  input [3:0]       rid_m6;
  input [31:0]      rdata_m6;
  input [1:0]       rresp_m6;
  input             rlast_m6;
  input             rvalid_m6;
  output            rready_m6;

  // Master Interface 7 Port

  // Write Address Channel
  output [3:0]                      awuser_m7;
  output [3:0]      awid_m7;
  output [31:0]     awaddr_m7;
  output [7:0]      awlen_m7;
  output [2:0]      awsize_m7;
  output [1:0]      awburst_m7;
  output            awlock_m7;
  output [3:0]      awcache_m7;
  output [2:0]      awprot_m7;
  output            awvalid_m7;
  output           awvalid_vect_m7;
  input             awready_m7;
  output [3:0]      aw_qv_m7;
   
  // Write Channel
  output  [31:0]    wdata_m7;
  output  [3:0]     wstrb_m7;
  output            wlast_m7;
  output            wvalid_m7;
  input             wready_m7;

  // Write Response Channel
  input [3:0]       bid_m7;
  input [1:0]       bresp_m7;
  input             bvalid_m7;
  output            bready_m7;

  // Read Address Channel
  output  [3:0]          aruser_m7;
  output  [3:0]     arid_m7;
  output  [31:0]    araddr_m7;
  output  [7:0]     arlen_m7;
  output  [2:0]     arsize_m7;
  output  [1:0]     arburst_m7;
  output            arlock_m7;
  output  [3:0]     arcache_m7;
  output  [2:0]     arprot_m7;
  output            arvalid_m7;
  output            arvalid_vect_m7;
  input             arready_m7;
  output  [3:0]     ar_qv_m7;
   
  // Read Channel
  input [3:0]       rid_m7;
  input [31:0]      rdata_m7;
  input [1:0]       rresp_m7;
  input             rlast_m7;
  input             rvalid_m7;
  output            rready_m7;

  // Master Interface 8 Port

  // Write Address Channel
  output [3:0]                      awuser_m8;
  output [3:0]      awid_m8;
  output [31:0]     awaddr_m8;
  output [7:0]      awlen_m8;
  output [2:0]      awsize_m8;
  output [1:0]      awburst_m8;
  output            awlock_m8;
  output [3:0]      awcache_m8;
  output [2:0]      awprot_m8;
  output            awvalid_m8;
  output           awvalid_vect_m8;
  input             awready_m8;
  output [3:0]      aw_qv_m8;
   
  // Write Channel
  output  [31:0]    wdata_m8;
  output  [3:0]     wstrb_m8;
  output            wlast_m8;
  output            wvalid_m8;
  input             wready_m8;

  // Write Response Channel
  input [3:0]       bid_m8;
  input [1:0]       bresp_m8;
  input             bvalid_m8;
  output            bready_m8;

  // Read Address Channel
  output  [3:0]          aruser_m8;
  output  [3:0]     arid_m8;
  output  [31:0]    araddr_m8;
  output  [7:0]     arlen_m8;
  output  [2:0]     arsize_m8;
  output  [1:0]     arburst_m8;
  output            arlock_m8;
  output  [3:0]     arcache_m8;
  output  [2:0]     arprot_m8;
  output            arvalid_m8;
  output            arvalid_vect_m8;
  input             arready_m8;
  output  [3:0]     ar_qv_m8;
   
  // Read Channel
  input [3:0]       rid_m8;
  input [31:0]      rdata_m8;
  input [1:0]       rresp_m8;
  input             rlast_m8;
  input             rvalid_m8;
  output            rready_m8;

  // Miscelaneous connections
  input             aclk;
  input             aresetn;

  //------------------------------------------------------------------------------
  // Wires 
  //------------------------------------------------------------------------------

  wire [8:0]           aw_enable;
  wire [8:0]           awready_s_int;
  wire [8:0]           wready_s_int;
  wire [8:0]           arready_s_int;
  wire [8:0]           awsel;
  wire [8:0]           arsel;
  wire [8:0]           tt_enable_wr;
  wire [8:0]           wr_enable;
  wire [8:0]           tt_enable_rd;
  wire [8:0]           bvalid_s_int;
  wire [35:0]           bid_s_int;
  wire [17:0]           bresp_s_int;
  wire [8:0]           rvalid_s_int;
  wire [8:0]           rlast_s_int;
  wire [35:0]           rid_s_int;
  wire [287:0]           rdata_s_int;
  wire [17:0]           rresp_s_int;


  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------


  //------------------------- Address channel routing -------------------------
  // AW - wire aw slave interface ports to all master interface port outputs,
  // rip off only the required valid bits to each port
  assign awuser_m0 = awuser_s;
  assign awid_m0 = awid_s;
  assign awaddr_m0 = awaddr_s;
  assign awlen_m0 = awlen_s;
  assign awsize_m0 = awsize_s;
  assign awburst_m0 = awburst_s;
  assign awlock_m0 = awlock_s;
  assign awcache_m0 = awcache_s;
  assign awprot_m0 = awprot_s;
  assign aw_qv_m0 = aw_qv_s;
  assign awvalid_m0 = awvalid_s & aw_enable[0];
  assign awvalid_vect_m0 = awvalid_vect_s[0] & aw_enable[0]; 

  assign awuser_m1 = awuser_s;
  assign awid_m1 = awid_s;
  assign awaddr_m1 = awaddr_s;
  assign awlen_m1 = awlen_s;
  assign awsize_m1 = awsize_s;
  assign awburst_m1 = awburst_s;
  assign awlock_m1 = awlock_s;
  assign awcache_m1 = awcache_s;
  assign awprot_m1 = awprot_s;
  assign aw_qv_m1 = aw_qv_s;
  assign awvalid_m1 = awvalid_s & aw_enable[1];
  assign awvalid_vect_m1 = awvalid_vect_s[1] & aw_enable[1]; 

  assign awuser_m2 = awuser_s;
  assign awid_m2 = awid_s;
  assign awaddr_m2 = awaddr_s;
  assign awlen_m2 = awlen_s;
  assign awsize_m2 = awsize_s;
  assign awburst_m2 = awburst_s;
  assign awlock_m2 = awlock_s;
  assign awcache_m2 = awcache_s;
  assign awprot_m2 = awprot_s;
  assign aw_qv_m2 = aw_qv_s;
  assign awvalid_m2 = awvalid_s & aw_enable[2];
  assign awvalid_vect_m2 = awvalid_vect_s[2] & aw_enable[2]; 

  assign awuser_m3 = awuser_s;
  assign awid_m3 = awid_s;
  assign awaddr_m3 = awaddr_s;
  assign awlen_m3 = awlen_s;
  assign awsize_m3 = awsize_s;
  assign awburst_m3 = awburst_s;
  assign awlock_m3 = awlock_s;
  assign awcache_m3 = awcache_s;
  assign awprot_m3 = awprot_s;
  assign aw_qv_m3 = aw_qv_s;
  assign awvalid_m3 = awvalid_s & aw_enable[3];
  assign awvalid_vect_m3 = awvalid_vect_s[3] & aw_enable[3]; 

  assign awuser_m4 = awuser_s;
  assign awid_m4 = awid_s;
  assign awaddr_m4 = awaddr_s;
  assign awlen_m4 = awlen_s;
  assign awsize_m4 = awsize_s;
  assign awburst_m4 = awburst_s;
  assign awlock_m4 = awlock_s;
  assign awcache_m4 = awcache_s;
  assign awprot_m4 = awprot_s;
  assign aw_qv_m4 = aw_qv_s;
  assign awvalid_m4 = awvalid_s & aw_enable[4];
  assign awvalid_vect_m4 = awvalid_vect_s[4] & aw_enable[4]; 

  assign awuser_m5 = awuser_s;
  assign awid_m5 = awid_s;
  assign awaddr_m5 = awaddr_s;
  assign awlen_m5 = awlen_s;
  assign awsize_m5 = awsize_s;
  assign awburst_m5 = awburst_s;
  assign awlock_m5 = awlock_s;
  assign awcache_m5 = awcache_s;
  assign awprot_m5 = awprot_s;
  assign aw_qv_m5 = aw_qv_s;
  assign awvalid_m5 = awvalid_s & aw_enable[5];
  assign awvalid_vect_m5 = awvalid_vect_s[5] & aw_enable[5]; 

  assign awuser_m6 = awuser_s;
  assign awid_m6 = awid_s;
  assign awaddr_m6 = awaddr_s;
  assign awlen_m6 = awlen_s;
  assign awsize_m6 = awsize_s;
  assign awburst_m6 = awburst_s;
  assign awlock_m6 = awlock_s;
  assign awcache_m6 = awcache_s;
  assign awprot_m6 = awprot_s;
  assign aw_qv_m6 = aw_qv_s;
  assign awvalid_m6 = awvalid_s & aw_enable[6];
  assign awvalid_vect_m6 = awvalid_vect_s[6] & aw_enable[6]; 

  assign awuser_m7 = awuser_s;
  assign awid_m7 = awid_s;
  assign awaddr_m7 = awaddr_s;
  assign awlen_m7 = awlen_s;
  assign awsize_m7 = awsize_s;
  assign awburst_m7 = awburst_s;
  assign awlock_m7 = awlock_s;
  assign awcache_m7 = awcache_s;
  assign awprot_m7 = awprot_s;
  assign aw_qv_m7 = aw_qv_s;
  assign awvalid_m7 = awvalid_s & aw_enable[7];
  assign awvalid_vect_m7 = awvalid_vect_s[7] & aw_enable[7]; 

  assign awuser_m8 = awuser_s;
  assign awid_m8 = awid_s;
  assign awaddr_m8 = awaddr_s;
  assign awlen_m8 = awlen_s;
  assign awsize_m8 = awsize_s;
  assign awburst_m8 = awburst_s;
  assign awlock_m8 = awlock_s;
  assign awcache_m8 = awcache_s;
  assign awprot_m8 = awprot_s;
  assign aw_qv_m8 = aw_qv_s;
  assign awvalid_m8 = awvalid_s & aw_enable[8];
  assign awvalid_vect_m8 = awvalid_vect_s[8] & aw_enable[8]; 

  assign awready_s_int[0] = awready_m0 & aw_enable[0];
  assign awready_s_int[1] = awready_m1 & aw_enable[1];
  assign awready_s_int[2] = awready_m2 & aw_enable[2];
  assign awready_s_int[3] = awready_m3 & aw_enable[3];
  assign awready_s_int[4] = awready_m4 & aw_enable[4];
  assign awready_s_int[5] = awready_m5 & aw_enable[5];
  assign awready_s_int[6] = awready_m6 & aw_enable[6];
  assign awready_s_int[7] = awready_m7 & aw_enable[7];
  assign awready_s_int[8] = awready_m8 & aw_enable[8]; 
  assign awready_s = |awready_s_int;


  // AR - wire ar slave interface ports to all master interface port outputs,
  // rip off only the required valid bits to each port
  assign aruser_m0 = aruser_s;
  assign arid_m0 = arid_s;
  assign araddr_m0 = araddr_s;
  assign arlen_m0 = arlen_s;
  assign arsize_m0 = arsize_s;
  assign arburst_m0 = arburst_s;
  assign arlock_m0 = arlock_s;
  assign arcache_m0 = arcache_s;
  assign arprot_m0 = arprot_s;
  assign ar_qv_m0 = ar_qv_s;
  assign arvalid_m0 = arsel[0];
  assign arvalid_vect_m0 = arvalid_vect_s[0];

  assign aruser_m1 = aruser_s;
  assign arid_m1 = arid_s;
  assign araddr_m1 = araddr_s;
  assign arlen_m1 = arlen_s;
  assign arsize_m1 = arsize_s;
  assign arburst_m1 = arburst_s;
  assign arlock_m1 = arlock_s;
  assign arcache_m1 = arcache_s;
  assign arprot_m1 = arprot_s;
  assign ar_qv_m1 = ar_qv_s;
  assign arvalid_m1 = arsel[1];
  assign arvalid_vect_m1 = arvalid_vect_s[1];

  assign aruser_m2 = aruser_s;
  assign arid_m2 = arid_s;
  assign araddr_m2 = araddr_s;
  assign arlen_m2 = arlen_s;
  assign arsize_m2 = arsize_s;
  assign arburst_m2 = arburst_s;
  assign arlock_m2 = arlock_s;
  assign arcache_m2 = arcache_s;
  assign arprot_m2 = arprot_s;
  assign ar_qv_m2 = ar_qv_s;
  assign arvalid_m2 = arsel[2];
  assign arvalid_vect_m2 = arvalid_vect_s[2];

  assign aruser_m3 = aruser_s;
  assign arid_m3 = arid_s;
  assign araddr_m3 = araddr_s;
  assign arlen_m3 = arlen_s;
  assign arsize_m3 = arsize_s;
  assign arburst_m3 = arburst_s;
  assign arlock_m3 = arlock_s;
  assign arcache_m3 = arcache_s;
  assign arprot_m3 = arprot_s;
  assign ar_qv_m3 = ar_qv_s;
  assign arvalid_m3 = arsel[3];
  assign arvalid_vect_m3 = arvalid_vect_s[3];

  assign aruser_m4 = aruser_s;
  assign arid_m4 = arid_s;
  assign araddr_m4 = araddr_s;
  assign arlen_m4 = arlen_s;
  assign arsize_m4 = arsize_s;
  assign arburst_m4 = arburst_s;
  assign arlock_m4 = arlock_s;
  assign arcache_m4 = arcache_s;
  assign arprot_m4 = arprot_s;
  assign ar_qv_m4 = ar_qv_s;
  assign arvalid_m4 = arsel[4];
  assign arvalid_vect_m4 = arvalid_vect_s[4];

  assign aruser_m5 = aruser_s;
  assign arid_m5 = arid_s;
  assign araddr_m5 = araddr_s;
  assign arlen_m5 = arlen_s;
  assign arsize_m5 = arsize_s;
  assign arburst_m5 = arburst_s;
  assign arlock_m5 = arlock_s;
  assign arcache_m5 = arcache_s;
  assign arprot_m5 = arprot_s;
  assign ar_qv_m5 = ar_qv_s;
  assign arvalid_m5 = arsel[5];
  assign arvalid_vect_m5 = arvalid_vect_s[5];

  assign aruser_m6 = aruser_s;
  assign arid_m6 = arid_s;
  assign araddr_m6 = araddr_s;
  assign arlen_m6 = arlen_s;
  assign arsize_m6 = arsize_s;
  assign arburst_m6 = arburst_s;
  assign arlock_m6 = arlock_s;
  assign arcache_m6 = arcache_s;
  assign arprot_m6 = arprot_s;
  assign ar_qv_m6 = ar_qv_s;
  assign arvalid_m6 = arsel[6];
  assign arvalid_vect_m6 = arvalid_vect_s[6];

  assign aruser_m7 = aruser_s;
  assign arid_m7 = arid_s;
  assign araddr_m7 = araddr_s;
  assign arlen_m7 = arlen_s;
  assign arsize_m7 = arsize_s;
  assign arburst_m7 = arburst_s;
  assign arlock_m7 = arlock_s;
  assign arcache_m7 = arcache_s;
  assign arprot_m7 = arprot_s;
  assign ar_qv_m7 = ar_qv_s;
  assign arvalid_m7 = arsel[7];
  assign arvalid_vect_m7 = arvalid_vect_s[7];

  assign aruser_m8 = aruser_s;
  assign arid_m8 = arid_s;
  assign araddr_m8 = araddr_s;
  assign arlen_m8 = arlen_s;
  assign arsize_m8 = arsize_s;
  assign arburst_m8 = arburst_s;
  assign arlock_m8 = arlock_s;
  assign arcache_m8 = arcache_s;
  assign arprot_m8 = arprot_s;
  assign ar_qv_m8 = ar_qv_s;
  assign arvalid_m8 = arsel[8];
  assign arvalid_vect_m8 = arvalid_vect_s[8];

  assign arready_s_int[0] = arready_m0 & arsel[0];
  assign arready_s_int[1] = arready_m1 & arsel[1];
  assign arready_s_int[2] = arready_m2 & arsel[2];
  assign arready_s_int[3] = arready_m3 & arsel[3];
  assign arready_s_int[4] = arready_m4 & arsel[4];
  assign arready_s_int[5] = arready_m5 & arsel[5];
  assign arready_s_int[6] = arready_m6 & arsel[6];
  assign arready_s_int[7] = arready_m7 & arsel[7];
  assign arready_s_int[8] = arready_m8 & arsel[8]; 
  assign arready_s = |arready_s_int;


  // Create a vector of valids for each master interface selection for
  // the transaction tracker 
  assign awsel[0] = awvalid_s & awvalid_vect_s[0];
  assign arsel[0] = arvalid_s & arvalid_vect_s[0];
  assign awsel[1] = awvalid_s & awvalid_vect_s[1];
  assign arsel[1] = arvalid_s & arvalid_vect_s[1];
  assign awsel[2] = awvalid_s & awvalid_vect_s[2];
  assign arsel[2] = arvalid_s & arvalid_vect_s[2];
  assign awsel[3] = awvalid_s & awvalid_vect_s[3];
  assign arsel[3] = arvalid_s & arvalid_vect_s[3];
  assign awsel[4] = awvalid_s & awvalid_vect_s[4];
  assign arsel[4] = arvalid_s & arvalid_vect_s[4];
  assign awsel[5] = awvalid_s & awvalid_vect_s[5];
  assign arsel[5] = arvalid_s & arvalid_vect_s[5];
  assign awsel[6] = awvalid_s & awvalid_vect_s[6];
  assign arsel[6] = arvalid_s & arvalid_vect_s[6];
  assign awsel[7] = awvalid_s & awvalid_vect_s[7];
  assign arsel[7] = arvalid_s & arvalid_vect_s[7];
  assign awsel[8] = awvalid_s & awvalid_vect_s[8];
  assign arsel[8] = arvalid_s & arvalid_vect_s[8];

  //--------------- Instantiate the active transaction trackers ---------------
  // Writes
  nic400_switch2_wr_st_tt_s0_ysyx_rv32 u_nic400_switch2_wr_st_tt_1_9m_ysyx_rv32 (
        // Outputs
        .aw_enable    (aw_enable),
        .tt_enable    (tt_enable_wr),
        .wr_enable    (wr_enable),
        // Inputs
        .asel         (awsel),
        .aready       (awready_s),
        .wvalid       (wvalid_s),
        .wready       (wready_s),
        .wlast        (wlast_s),
        .resp_valid   (bvalid_s),
        .resp_ready   (bready_s),
        // Miscelaneous connections
        .aclk         (aclk),
        .aresetn      (aresetn)
  );

  // Reads
  nic400_switch2_rd_st_tt_s0_ysyx_rv32 u_nic400_switch2_rd_st_tt_1_9m_ysyx_rv32 (
        // Outputs
        .tt_enable    (tt_enable_rd),
        // Inputs

        .asel         (arsel),
        .aready       (arready_s),
        .resp_valid   (rvalid_s),
        .resp_last    (rlast_s),
        .resp_ready   (rready_s),

        // Miscelaneous connections
        .aclk         (aclk),
        .aresetn      (aresetn)
  );

  //-------------------------- Write channel routing --------------------------
  assign wdata_m0 = wdata_s;
  assign wstrb_m0 = wstrb_s;
  assign wlast_m0 = wlast_s;
  assign wvalid_m0 = wvalid_s & wr_enable[0];
  assign wready_s_int[0] = wready_m0 & wr_enable[0];

  assign wdata_m1 = wdata_s;
  assign wstrb_m1 = wstrb_s;
  assign wlast_m1 = wlast_s;
  assign wvalid_m1 = wvalid_s & wr_enable[1];
  assign wready_s_int[1] = wready_m1 & wr_enable[1];

  assign wdata_m2 = wdata_s;
  assign wstrb_m2 = wstrb_s;
  assign wlast_m2 = wlast_s;
  assign wvalid_m2 = wvalid_s & wr_enable[2];
  assign wready_s_int[2] = wready_m2 & wr_enable[2];

  assign wdata_m3 = wdata_s;
  assign wstrb_m3 = wstrb_s;
  assign wlast_m3 = wlast_s;
  assign wvalid_m3 = wvalid_s & wr_enable[3];
  assign wready_s_int[3] = wready_m3 & wr_enable[3];

  assign wdata_m4 = wdata_s;
  assign wstrb_m4 = wstrb_s;
  assign wlast_m4 = wlast_s;
  assign wvalid_m4 = wvalid_s & wr_enable[4];
  assign wready_s_int[4] = wready_m4 & wr_enable[4];

  assign wdata_m5 = wdata_s;
  assign wstrb_m5 = wstrb_s;
  assign wlast_m5 = wlast_s;
  assign wvalid_m5 = wvalid_s & wr_enable[5];
  assign wready_s_int[5] = wready_m5 & wr_enable[5];

  assign wdata_m6 = wdata_s;
  assign wstrb_m6 = wstrb_s;
  assign wlast_m6 = wlast_s;
  assign wvalid_m6 = wvalid_s & wr_enable[6];
  assign wready_s_int[6] = wready_m6 & wr_enable[6];

  assign wdata_m7 = wdata_s;
  assign wstrb_m7 = wstrb_s;
  assign wlast_m7 = wlast_s;
  assign wvalid_m7 = wvalid_s & wr_enable[7];
  assign wready_s_int[7] = wready_m7 & wr_enable[7];

  assign wdata_m8 = wdata_s;
  assign wstrb_m8 = wstrb_s;
  assign wlast_m8 = wlast_s;
  assign wvalid_m8 = wvalid_s & wr_enable[8];
  assign wready_s_int[8] = wready_m8 & wr_enable[8];
  
  assign wready_s = |wready_s_int;


  //------------- Instantiate the response channel arbitration modules---------

  // For single slave or no cyclic dependancy scheme configurations there is no
  // arbitration required for the return channels as only one master interface
  // can have outstanding transactions at any time.


  //--------------- Instantiate the response channel routing modules-----------
  // Writes
  assign bid_s_int[3:0] = bid_m0 & {4{tt_enable_wr[0]}};
  assign bresp_s_int[1:0] = bresp_m0 & {2{tt_enable_wr[0]}};
  assign bvalid_s_int[0] = bvalid_m0 & tt_enable_wr[0];
  assign bready_m0 = bready_s & tt_enable_wr[0];

  assign bid_s_int[7:4] = bid_m1 & {4{tt_enable_wr[1]}};
  assign bresp_s_int[3:2] = bresp_m1 & {2{tt_enable_wr[1]}};
  assign bvalid_s_int[1] = bvalid_m1 & tt_enable_wr[1];
  assign bready_m1 = bready_s & tt_enable_wr[1];

  assign bid_s_int[11:8] = bid_m2 & {4{tt_enable_wr[2]}};
  assign bresp_s_int[5:4] = bresp_m2 & {2{tt_enable_wr[2]}};
  assign bvalid_s_int[2] = bvalid_m2 & tt_enable_wr[2];
  assign bready_m2 = bready_s & tt_enable_wr[2];

  assign bid_s_int[15:12] = bid_m3 & {4{tt_enable_wr[3]}};
  assign bresp_s_int[7:6] = bresp_m3 & {2{tt_enable_wr[3]}};
  assign bvalid_s_int[3] = bvalid_m3 & tt_enable_wr[3];
  assign bready_m3 = bready_s & tt_enable_wr[3];

  assign bid_s_int[19:16] = bid_m4 & {4{tt_enable_wr[4]}};
  assign bresp_s_int[9:8] = bresp_m4 & {2{tt_enable_wr[4]}};
  assign bvalid_s_int[4] = bvalid_m4 & tt_enable_wr[4];
  assign bready_m4 = bready_s & tt_enable_wr[4];

  assign bid_s_int[23:20] = bid_m5 & {4{tt_enable_wr[5]}};
  assign bresp_s_int[11:10] = bresp_m5 & {2{tt_enable_wr[5]}};
  assign bvalid_s_int[5] = bvalid_m5 & tt_enable_wr[5];
  assign bready_m5 = bready_s & tt_enable_wr[5];

  assign bid_s_int[27:24] = bid_m6 & {4{tt_enable_wr[6]}};
  assign bresp_s_int[13:12] = bresp_m6 & {2{tt_enable_wr[6]}};
  assign bvalid_s_int[6] = bvalid_m6 & tt_enable_wr[6];
  assign bready_m6 = bready_s & tt_enable_wr[6];

  assign bid_s_int[31:28] = bid_m7 & {4{tt_enable_wr[7]}};
  assign bresp_s_int[15:14] = bresp_m7 & {2{tt_enable_wr[7]}};
  assign bvalid_s_int[7] = bvalid_m7 & tt_enable_wr[7];
  assign bready_m7 = bready_s & tt_enable_wr[7];

  assign bid_s_int[35:32] = bid_m8 & {4{tt_enable_wr[8]}};
  assign bresp_s_int[17:16] = bresp_m8 & {2{tt_enable_wr[8]}};
  assign bvalid_s_int[8] = bvalid_m8 & tt_enable_wr[8];
  assign bready_m8 = bready_s & tt_enable_wr[8];
  // Or the masked vectors to provide the mux outputs
  assign bvalid_s = |bvalid_s_int;
  assign bid_s = bid_s_int[3:0]
                 | bid_s_int[7:4]
                 | bid_s_int[11:8]
                 | bid_s_int[15:12]
                 | bid_s_int[19:16]
                 | bid_s_int[23:20]
                 | bid_s_int[27:24]
                 | bid_s_int[31:28]
                 | bid_s_int[35:32];
  assign bresp_s = bresp_s_int[1:0]
                 | bresp_s_int[3:2]
                 | bresp_s_int[5:4]
                 | bresp_s_int[7:6]
                 | bresp_s_int[9:8]
                 | bresp_s_int[11:10]
                 | bresp_s_int[13:12]
                 | bresp_s_int[15:14]
                 | bresp_s_int[17:16];

  // Reads
  assign rid_s_int[3:0] = rid_m0 & {4{tt_enable_rd[0]}};
  assign rdata_s_int[31:0] = rdata_m0 & {32{tt_enable_rd[0]}};
  assign rresp_s_int[1:0] = rresp_m0 & {2{tt_enable_rd[0]}};
  assign rlast_s_int[0] = rlast_m0 & tt_enable_rd[0];
  assign rvalid_s_int[0] = rvalid_m0 & tt_enable_rd[0];
  assign rready_m0 = rready_s & tt_enable_rd[0];

  assign rid_s_int[7:4] = rid_m1 & {4{tt_enable_rd[1]}};
  assign rdata_s_int[63:32] = rdata_m1 & {32{tt_enable_rd[1]}};
  assign rresp_s_int[3:2] = rresp_m1 & {2{tt_enable_rd[1]}};
  assign rlast_s_int[1] = rlast_m1 & tt_enable_rd[1];
  assign rvalid_s_int[1] = rvalid_m1 & tt_enable_rd[1];
  assign rready_m1 = rready_s & tt_enable_rd[1];

  assign rid_s_int[11:8] = rid_m2 & {4{tt_enable_rd[2]}};
  assign rdata_s_int[95:64] = rdata_m2 & {32{tt_enable_rd[2]}};
  assign rresp_s_int[5:4] = rresp_m2 & {2{tt_enable_rd[2]}};
  assign rlast_s_int[2] = rlast_m2 & tt_enable_rd[2];
  assign rvalid_s_int[2] = rvalid_m2 & tt_enable_rd[2];
  assign rready_m2 = rready_s & tt_enable_rd[2];

  assign rid_s_int[15:12] = rid_m3 & {4{tt_enable_rd[3]}};
  assign rdata_s_int[127:96] = rdata_m3 & {32{tt_enable_rd[3]}};
  assign rresp_s_int[7:6] = rresp_m3 & {2{tt_enable_rd[3]}};
  assign rlast_s_int[3] = rlast_m3 & tt_enable_rd[3];
  assign rvalid_s_int[3] = rvalid_m3 & tt_enable_rd[3];
  assign rready_m3 = rready_s & tt_enable_rd[3];

  assign rid_s_int[19:16] = rid_m4 & {4{tt_enable_rd[4]}};
  assign rdata_s_int[159:128] = rdata_m4 & {32{tt_enable_rd[4]}};
  assign rresp_s_int[9:8] = rresp_m4 & {2{tt_enable_rd[4]}};
  assign rlast_s_int[4] = rlast_m4 & tt_enable_rd[4];
  assign rvalid_s_int[4] = rvalid_m4 & tt_enable_rd[4];
  assign rready_m4 = rready_s & tt_enable_rd[4];

  assign rid_s_int[23:20] = rid_m5 & {4{tt_enable_rd[5]}};
  assign rdata_s_int[191:160] = rdata_m5 & {32{tt_enable_rd[5]}};
  assign rresp_s_int[11:10] = rresp_m5 & {2{tt_enable_rd[5]}};
  assign rlast_s_int[5] = rlast_m5 & tt_enable_rd[5];
  assign rvalid_s_int[5] = rvalid_m5 & tt_enable_rd[5];
  assign rready_m5 = rready_s & tt_enable_rd[5];

  assign rid_s_int[27:24] = rid_m6 & {4{tt_enable_rd[6]}};
  assign rdata_s_int[223:192] = rdata_m6 & {32{tt_enable_rd[6]}};
  assign rresp_s_int[13:12] = rresp_m6 & {2{tt_enable_rd[6]}};
  assign rlast_s_int[6] = rlast_m6 & tt_enable_rd[6];
  assign rvalid_s_int[6] = rvalid_m6 & tt_enable_rd[6];
  assign rready_m6 = rready_s & tt_enable_rd[6];

  assign rid_s_int[31:28] = rid_m7 & {4{tt_enable_rd[7]}};
  assign rdata_s_int[255:224] = rdata_m7 & {32{tt_enable_rd[7]}};
  assign rresp_s_int[15:14] = rresp_m7 & {2{tt_enable_rd[7]}};
  assign rlast_s_int[7] = rlast_m7 & tt_enable_rd[7];
  assign rvalid_s_int[7] = rvalid_m7 & tt_enable_rd[7];
  assign rready_m7 = rready_s & tt_enable_rd[7];

  assign rid_s_int[35:32] = rid_m8 & {4{tt_enable_rd[8]}};
  assign rdata_s_int[287:256] = rdata_m8 & {32{tt_enable_rd[8]}};
  assign rresp_s_int[17:16] = rresp_m8 & {2{tt_enable_rd[8]}};
  assign rlast_s_int[8] = rlast_m8 & tt_enable_rd[8];
  assign rvalid_s_int[8] = rvalid_m8 & tt_enable_rd[8];
  assign rready_m8 = rready_s & tt_enable_rd[8];
 // Or the masked vectors to provide the mux outputs 
  assign rvalid_s = |rvalid_s_int;
  assign rlast_s = |rlast_s_int;
  assign rid_s = rid_s_int[3:0]
                 | rid_s_int[7:4]
                 | rid_s_int[11:8]
                 | rid_s_int[15:12]
                 | rid_s_int[19:16]
                 | rid_s_int[23:20]
                 | rid_s_int[27:24]
                 | rid_s_int[31:28]
                 | rid_s_int[35:32];
  assign rresp_s = rresp_s_int[1:0]
                 | rresp_s_int[3:2]
                 | rresp_s_int[5:4]
                 | rresp_s_int[7:6]
                 | rresp_s_int[9:8]
                 | rresp_s_int[11:10]
                 | rresp_s_int[13:12]
                 | rresp_s_int[15:14]
                 | rresp_s_int[17:16];
  assign rdata_s = rdata_s_int[31:0]
                 | rdata_s_int[63:32]
                 | rdata_s_int[95:64]
                 | rdata_s_int[127:96]
                 | rdata_s_int[159:128]
                 | rdata_s_int[191:160]
                 | rdata_s_int[223:192]
                 | rdata_s_int[255:224]
                 | rdata_s_int[287:256];

  endmodule

//  --=============================== End ====================================--

